Daughter board for a prototyping system

ABSTRACT

A daughter board ( 405 ) is provided for a prototyping system ( 100 ). The daughter board includes a first surface for facing a mother board ( 115 ) of the prototyping system, and a second surface opposed thereto. The daughter board further includes a connector ( 410 ) for a corresponding socket ( 210 ) of the mother board arranged on the first surface. The connector includes multiple elements ( 410   t-   410   b ), each one including an insulating support and multiple leads. The daughter board also includes multiple contacts ( 482 ) for corresponding functional terminals of a programmable device ( 420 ) arranged on the second surface. Each contact is connected to a corresponding lead ( 476 ) of the connector. The elements of the connector are arranged along the edges of a regular polygon.

FIELD OF THE INVENTION

The present invention relates to a daughter board for a prototypingsystem.

BACKGROUND OF THE INVENTION

Prototyping systems are commonly used for validating electroniccircuits. A prototyping system makes it possible to create a physicalimplementation of the electronic circuit under validation (a prototype).The prototype is tested in order to determine whether the electroniccircuit exhibits the desired features; for example, this is an essentialstep of the design process of any complex electronic circuit, such as adigital ASIC (Application Specific Integrated Circuit).

Typically, the prototype is created scattering the electronic circuitacross several FPGAs (Field-Programmable Gate Arrays) that are connectedtogether. A known solution is that of employing a breadboard, whichconsists of a printed circuit board that is custom designed in order tomeet the specific routing requirements of the prototype. The FPGAs areplaced onto the breadboard and connected together through conductivetracks. This structure allows the prototype to run at a frequency thatis close to the one of the actual electronic circuit (real-timeprototyping).

However, the making of the breadboard is an expensive process, in termsof both manpower costs and development time; moreover, it is notpossible to re-use the breadboard for a different prototype. Thesolution described above is quite rigid, since the breadboard cannot bealtered in any way.

A different solution is that of using a field-programmable printedcircuit board, which is provided with a grid of holes for plugging inthe FPGAS. These holes are grouped into sections, with all holes in asection leading to corresponding pins of a switch matrix; the switchmatrices communicate between themselves with direct hardwiredconnections. This architecture provides a high routing flexibility,since a complete interconnectivity of the FPGAs can be obtained bysuitably configuring the switch matrices.

However, in the solution described above each signal to be transmittedbetween two FPGAs must go through some switches. This introducesconsiderable delays, which reduce the operative frequency of theprototype; therefore, the prototype can only run at a speedsignificantly lower than the one of the actual electronic circuit.

In many cases, a real world target system in which the electroniccircuit must operate has timing constraints; particularly, somecomponents of the target system cannot be slowed down too much, forexample because an internal PLL does not work below a thresholdfrequency. As a consequence, it is not possible to connect the prototypeto other systems directly; this does not allow the prototype to beoperated and tested under normal working conditions.

Similar drawbacks are also suffered using alternative topologies forinterconnecting the FPGAs. For example, known prototyping systemsenvisage a mesh (wherein each FPGA is connected to the nearest-neighbourFPGAs, possibly through one or more hops), a cross-bar (wherein theFPGAs are connected to a routing-only element, possibly with ahierarchical structure), virtual wires or pin multiplexing (whereinsignals are multiplexed over a reduced number of physical wires), andthe like.

Modular systems have been also proposed. In these systems, the FPGAs aremounted on daughter boards that are connected together or to a motherboard in order to attain the desired configuration of the prototypingsystem.

However, none of the daughter boards known in the art has a structurethat is specifically tailored to the use in a very high-speedprototyping system. Therefore, the daughter boards have a detrimentalimpact on the performance of the whole prototyping system. Thisintroduces additional delays, which further reduce the operativefrequency of the prototype.

SUMMARY OF THE INVENTION

It is an object of the present invention to overcome the above-mentioneddrawbacks. In order to achieve this object, a daughter board for aprototyping system as set out in the first claim is proposed.

Briefly, the present invention provides a daughter board for aprototyping system having a first surface for facing a mother board ofthe prototyping system and a second surface opposed thereto andincluding a connector for a corresponding socket of the mother boardarranged on the first surface, the connector consisting of a pluralityof elements each one including an insulating support and a plurality ofleads, and a plurality of contacts for corresponding functionalterminals of a programmable device arranged on the second surface, eachcontact being connected to a corresponding lead of the connector,wherein the elements of the connector are arranged along the edges of aregular polygon.

Moreover, the present invention also provides a prototyping systemincluding the daughter board.

BRIEF DESCRIPTION OF DRAWINGS

Further features and the advantages of the solution according to thepresent invention will be made clear by the following description of apreferred embodiment thereof, given purely by way of a non-restrictiveindication, with reference to the attached figures, in which:

FIG. 1 a is a prospective view of a prototyping system in which thedaughter board of the invention can be used;

FIG. 1 b depicts a back-plane of the prototyping system in a schematicview;

FIG. 2 shows a mother board of the prototyping system,

FIGS. 3 a and 3 b are a schematic block diagram of the mother board andof a particular thereof, respectively;

FIG. 4 a depicts the daughter board;

FIG. 4 b is a partially cut away view from below of the daughter board;

FIG. 5 shows a different daughter board of the prototyping system; and

FIG. 6 is a cross-section view of the mother board with two daughterboards and one debugging board.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference in particular to FIG. 1 a, there is shown a system 100used as a physical platform for the fast prototyping of an electroniccircuit. The prototyping system 100 includes a back-plane 105, whichconsists of a multi-layer printed circuit board including supports forcommunicating with a host computer (not shown in the figure), both fordownloading programming and for uploading data captured during aprototyping process.

The back-plane 105 has a plurality of slots 110 a, 110 b, 110 c and 110d arranged on a front surface thereof (four in the example shown in thefigure). A mother board 115 a, 115 b, 115 c and 115 d is plugged intothe respective slot 110 a, 110 b, 110 c and 110 d. The back-plane 105 isalso provided with several system boards, which are plugged intocorresponding slots arranged on a rear surface of the back-plane 105,such as a compact PCI single board computer 120, a compact PCI carrier125, and a clock board 130. Two daughter bards 135 a and 135 b (such ascross-bar boards) can be plugged into corresponding sockets on the rearsurface of the back-plane 105; the cross-bar boards 135 a, 135 b arearranged along a diagonal of the back-plane 105.

Similar considerations apply if the back-plane has a different number ofslots for the mother boards, if the mother boards and the system boardsare all arranged on the same surface of the back-plane, if differentsystem boards are used, if the sockets are used for plugging indifferent components (such as a bridge), and the like.

Considering now the front surface of the back-plane 105 shown in theFIG. 1 b, each slot 110 i (with i=a . . . d) consists of four slotelements 110 ia, 110 ib, 110 ic and 110 id. The slot elements 110 aa and110 ba, are connected to a PCI bus 140 a (associated with the boards120, 125 mounted on the rear surface of the back-plane 105); the slotelements 110 ca and 110 da are connected to each other directly. Theslot elements 110 bd, 110 cd and 110 dd are likewise connected to afurther bus 140 b (for example of the ISA type). The clock board 130generates a plurality of global clock signals, which are distributed toall the slots 110 a-110 d by means of a balanced tree of conductivetracks on the back-plane 105.

Each cross-bar board 135 a, 135 b is plugged into a respective socket,which is square-shaped and has a top element 145 at, 145 bt and a rightelement 145 ar, 145 br moving counter clockwise from an insertion key147 a, 147 b (for a reference key of the cross-bar board 135 a, 135 b),and a left element 145 al, 145 bl and a bottom element 145 ab, 145 bbmoving clockwise from the insertion key 147 a, 147 b. The sockets(denoted as a whole with 145 a and 145 b) are turned in order to havethe insertion keys facing to each other.

The socket element 145 at is connected to the slot element 110 cb, thesocket element 145 al is connected to the slot element 110 db, thesocket element 145 ab is connected to the slot element 110 ab, and thesocket element 145 ar is connected to the slot element 110 bb. On theother hand, the socket element 145 bt is connected to the slot element110 bc, the socket element 145 bl is connected to the slot element 110ac, the socket element 145 bb is connected to the slot element 110 dc,and the socket element 145 br is connected to the slot element 110 cc.

Similar considerations apply if the back-plane has a differentstructure, if each slot consists of a different number of elements (downto a single one), if a different number of cross-bar boards and buses isenvisaged (down to a single cross-bar board and/or a single bus), if thebuses are of a different type or have a different length, and so on.

Considering now FIG. 2, a generic mother board 115 consists of amulti-layer printed circuit board (for example with 16 layers) having anedge connector formed by four elements 205 a, 205 b, 205 c and 205 d,which are plugged into the corresponding slot elements of theback-plane. The mother board 115 is provided with four sockets, whichare arranged at respective corners of a rectangle on a front surface ofthe mother board 115. The i-th socket (with i=a . . . d) issquare-shaped and has a left element 210 il and a bottom element 210 ibmoving counter clockwise from an insertion key 212 i, and a top element210 it and a right element 210 ir moving clockwise from the insertionkey 212 i. The sockets 210 a-210 d are turned in order to have theinsertion keys 212 a-212 d inward-looking the rectangle along which thesockets 210 a-210 d are arranged.

A bank of electronic switches is placed around the respective socket(denoted as a whole with 210 a, 210 b, 210 c and 210 d). The i-th bankof switches consists of a left set 215 il, a bottom set 215 ib, a topset 210 it and a right set 210 ir, which are associated with therespective socket elements 210 il, 210 ib, 210 it and 210 ir. Theswitches (denoted as a whole with 215 a, 215 b, 215 c and 215 d) arecontrolled by one or more banks of flash E²PROMs 220 a, 220 b, 220 c and220 d, respectively, which are mounted onto the mother board 115 insidethe corresponding sockets 210 a, 210 b, 210 c and 210 d.

Forward sockets 225 a and 225 d are provided on the front surface of themother board 115 (to the left of the sockets 210 a and 210 d,respectively); backward sockets 230 a and 230 d are provided on a rearsurface of the mother board 115 (to the right of the forward sockets 225a and 225 d, respectively), and further forward sockets 235 a and 235 dare placed on the front surface of the mother board 115 (to the right ofthe sockets 210 a and 210 d, respectively). Moreover, further backwardsockets 240 b and 240 c are placed on the rear surface of the motherboard 115 (to the left of the sockets 210 b and 210 c, respectively).

The forward sockets 225 a, 225 d, 235 a and 235 d are used to connectthe mother board 115 to a next adjacent mother board (facing the motherboard 115); the backward sockets 230 a, 230 d, 240 b and 240 c arelikewise used to connect the mother board 115 to a previous adjacentmother board. In particular, each forward socket is connected to thecorresponding backward socket of the next mother board by means of aflat, flexible printed circuit 245 terminating with mating connectors(as shown in the figure for the forward socket 225 d).

The forward and backward sockets increase the connectivity capability ofthe prototyping system; the interconnection of the mother boards isfacilitated by their arrangement (with each mother board extendingperpendicularly from the back-plane and facing the adjacent motherboard). Advantageously, the use of the flexible printed circuits (with atransmission time of a few ns) does not introduce any slow down of thesystem. Moreover, the cross-bar boards and the buses on the back-planefurther increase the connectivity capability of the prototyping system.

Alternatively, the mother boards are connected together in a differentway, the mother boards are arranged elsewhere (for example extendingfrom both the surfaces of the back-plane), no backward and forwardsockets are provided on the mother boards (being connected together onlyvia the back-plane), or the prototyping system consists of a singlemother board (without any back-plane).

With reference to FIG. 3 a, each socket element consists for example of228 female leads, or holes, and 6 power female elements for providingthree distinct power supply voltages; the holes are numbered (from 1 to228) starting from the insertion key and moving counter clockwise alongthe left and bottom socket elements and moving clockwise along the topand right socket elements.

Each edge connector 205 a-d consists of 228 male leads, or pins, and 6power male elements; the pins of the edge connector elements 205 a, 205c are numbered from the bottom to the top, whereas the pins of the edgeconnector elements 205 b, 205 d are numbered from the top to the bottom.The edge connector elements 205 a, 205 d allow the mother board 115 toaccess the respective buses provided on the back-plane, and the edgeconnector elements 205 b, 205 c allow the mother board 115 to access therespective cross-bar boards plugged into the back-plane.

A connection 310 ca extends between the socket element 210 cb and theedge connector element 205 a, and a connection 310 bd extends betweenthe socket element 210 br and the edge connector element 205 d; aconnection 310 cb extends between the socket element 210 cr and the edgeconnector element 205 b, and a connection 310 bc extends between thesocket element 210 bb and the edge connector element 205 c.

Each forward and backward socket consists of 228 pins; the pins of theforward sockets 225 a, 235 a and of the backward sockets 230 a, 230 bare numbered from the bottom to the top, whereas the pins of the forwardsockets 225 d, 235 d and of the backward sockets 230 d, 230 c arenumbered from the top to the bottom. The forward and backward socketsare connected to corresponding socket elements. Particularly, aconnection 315 a extends between the socket element 210 ar and thebackward socket 230 a, and a connection 315 d extends between the socketelement 210 db and the backward socket 230 d; a connection 320 a extendsbetween the socket element 210 ab and the forward socket 225 a, aconnection 320 d extends between the socket element 210 dr and theforward socket 225 d, a connection 325 a extends between the socketelement 210 al and the forward socket 235 a, and a connection 325 dextends between the socket element 210 dt and the forward socket 235 d.Moreover, a connection 330 b extends between the socket element 210 btand the backward socket 240 b, and a connection 330 c extends betweenthe socket element 210 cl and the backward socket 240 c.

The mother board 115 further includes several point-to-point connectionsfor pairs of the sockets 210 a-d. Particularly, a connection 335 ab-brextends between the socket elements 210 ab and 210 br, a connection 335bb-cr extends between the socket elements 210 bb and 210 cr, aconnection 335 cb-dr extends between the socket elements 210 cb and 210dr, and a connection 335 db-ar extends between the socket elements 210db and 210 ar. Moreover, a connection 335 al-ct extends between thesocket elements 210 al and 210 ct, a connection 335 at-cl extendsbetween the socket elements 210 at and 210 cl, a connection 335 bt-dlextends between the socket elements 210 bt and 210 dl, and a connection335 bl-dt extends between the socket elements 210 bl and 210 dt.Moreover, the socket elements 210 at, 210 dl, 210 bl and 210 ct arecoupled to a bus connection 337.

The above-described connections are implemented by means of one or moreconductive tracks (each one provided on a corresponding layer of themother board 115), which are coupled through via-holes.

Similar considerations apply if the mother board has a different numberof edge connector elements, if the switches and the memories are placedelsewhere, if the mother board is provided with a different number offorward and backward sockets, if the sockets are coupled in a differentmanner with the edge connectors, the backward and forward sockets, orthe other sockets, and the like.

The holes of each socket element are selectively connected to one ormore of the corresponding connections by means of the respectiveswitches. For example, as shown in FIG. 3 b, each hole of the socketelement 210 ab is connected (by means of a conductive track) to aterminal of a first and a second of the switches 215 ab; the otherterminal of the first switch is connected to a line of the connection320 a, and the other terminal of the second switch is connected to aline of the connection 335 ab-br.

The two switches associated with each hole of the socket element 210 ab(implemented for example by means of pass-transistors) are controlled byrespective signals provided by the memory 220 a; for example, a bitstored in the memory 220 a controls the switch in an open or closedcondition when the bit has the value 0 or 1, respectively. In this way,the combinations 01 and 10 alternatively connect the hole of the socketelement 210 ab to the corresponding line of the connection 320 a or ofthe connection 335 ab-br, respectively, whereas the combination 00insulates the hole of the socket element 210 ab from both the connection320 a and the connection 335 ab-br (the combination 11, connecting thehole of the socket element 210 ab simultaneously to the connection 320 aand to the connection 335 ab-br, is preferably not used). The provisionof two switches results in a good compromise between flexibility andsimplicity.

Advantageously, the socket element 210 ab is split into several sets ofsequential holes (for example 28 sets each one of 8 holes, with theremaining 4 holes reserved for test purpose). All the switches 215 abassociated with the holes of each set are controlled by the same pair ofbits provided by the memory 220 a; in this way, the number of signalsrequired is strongly reduced, however maintaining a good flexibility ofthe structure.

Similar considerations apply if the switches are implemented bydifferent electronic components, if each hole of the sockets on themother board is connected to three or more switches, if each bitcontrols a different number of switches (down to a single one), if thesame signal controls the corresponding switches at both ends of eachpoint-to-point connection (with memories of lower capacity, but with amore complex routing of the control signals), and the like.

Two explanatory examples of daughter boards for FPGA (FIGS. 4 a and 4 b)and for microprocessor (FIG. 5), respectively, are now described indetail. Considering in particular FIG. 4 a, the prototyping systemincludes one or more daughter boards 405, which are mounted onto themother board. A connector is arranged on a lower surface of the daughterboard 405, and a socket is arranged on an upper surface of the daughterboard 405 (inside the connector in plan view).

The connector consists of a top element 410 t and a right element 410 rmoving counter clockwise from a reference key 417 (for the insertion keyof a corresponding socket of the mother board), and a left element 410 land a bottom element 410 b moving clockwise from the reference key 417(looking at the daughter board 405 from below). Similarly, the socketconsists of a left element 415 l and a bottom element 415 b movingcounter clockwise from the reference key 417, and a top element 415 tand a right element 415 r moving clockwise from the reference key 417(looking at the daughter board 405 from above). The elements of theconnector (denoted as a whole with 410) and the elements of the socket(denoted as a whole with 415) are arranged along concentric squares.

Each connector element consists of 228 pins and 6 power male elements(matching a corresponding socket element of the mother board), and eachsocket element consists of 228 holes and 6 power female elements; thepins and the power male elements of the connector 410 are coupled withcorresponding holes and power female elements of the socket 415 throughconductive tracks and via-holes.

An FPGA 420 and an E²PROM 425 are mounted on the upper surface of thedaughter board 405. Particularly, the daughter board 405 is providedwith a plurality of conductive pads for surface mounting correspondingterminals of the FPGA 420 and of the memory 425 (for example of the ballgrid array type). The memory 425 is used to configure the FPGA 420, towhich it is connected through conductive tracks (and via-holes). TheFPGA 420 has a reference corner (identified by a chamfer), which facesthe insertion key 417.

Two power converters 440 a and 440 b are mounted on the lower surface ofthe daughter board 405 (at opposed corners thereof). The converters 440a,b are connected to the power male elements of the connector 410 (forreceiving the power supply voltages provided by the back-plane throughthe mother board); the converter 440 a and the converter 440 b suppliesthe FPGA 420 and the memory 425, respectively (for example with avoltage of lower value). The power male elements with the associatedconverters make it possible to use devices that require a power supplyvoltage of any value.

The pads of the daughter board 405 (on which the FPGA 420 is mounted)are connected to corresponding pins of the connector 410 and tocorresponding holes of the socket 415. In this way, functional terminalsof the FPGA 420 (distinct from power supply terminals connected to theconverter 440 a and configuration terminals connected to the memory 425)are connected to both the connector 410 and the socket 415.

One to four auxiliary boards 450 (only one shown in the figure) aremounted onto the daughter board 405. A connector element 455 and anopposed socket element 460 are arranged on a lower surface and on anupper surface, respectively, of the auxiliary board 450. The connectorelement 455 consists of 228 pins and 6 power male elements matching acorresponding element of the socket 415, and the socket element 460consists of 228 holes (without any power element). The pins of theconnector element 455 are coupled with corresponding holes of the socketelement 460 through via-holes.

The auxiliary board 450 carries local resources (such as memory modules)used by the FPGA 420. Particularly, both the lower surface and the uppersurface of the auxiliary board 405 are provided with a plurality ofconductive pads for surface mounting corresponding terminals of localmemory modules 470 (four on both surfaces in the example shown in thefigure). The pads of the auxiliary board 450 are connected tocorresponding pins of the connector element 455 and to correspondingholes of the socket element 460; in this way, functional terminals ofthe local memories 470 (distinct from power supply terminals connectedto the power male elements of the connector 455) are connected tocorresponding functional terminals of the FPGA 420.

Similar considerations apply if the daughter board has a differentstructure, if the reference key is replaced by an equivalent mountingelement, if the socket has a different number of elements (down to asingle element), if the pads are replaced by equivalent contacts, if thedaughter board carries an MPGA (or one or more equivalent hardwareprogrammable devices, for which it is possible to configure the internalphysical connections), if no power converter is employed, if theauxiliary board has a different structure, if it carries a differentnumber of memory modules (down to a single one) or any other devicewhich is locally used by the FPGA, and so on.

As shown in FIG. 4 b, each connector element 410 t, 410 r, 410 b and 410l consists of an elongated insulating support having a first free end(identified by a reference key 473 t, 473 r, 473 b and 473 l,respectively) and a second free end opposed thereto. The first free endsof the connector elements 415 t and 415 l are close to the reference key417; the first free ends of the connector elements 410 r and 410 b areclose to the second free ends of the connector elements 410 t and 410 l,respectively.

Each connector element 410 t-410 b includes two parallel rows of pins476 (an internal one and an external one). The pins 476 are numberedfrom the reference key 473 t-473 b, alternating a pin of the externalrow and a pin of the internal row. Therefore, the external row consistsof the odd pins from 1 to 227, whereas the internal row consists of theeven pins from 2 to 228. The connector element 410 t-410 b furtherincludes a row of power male elements 478, which is arranged between thetwo parallel rows of pins 476. Each power male element 478 consists offive leads, or blades. The blades are numbered from the reference key473 t-473 b, so that the first, second, third, fourth, fifth and sixthpower male elements are formed by the blades 229-233, 234-238, 239-243,244-248, 249-253 and 254-259, respectively.

A matrix of pads 482 (on the opposed surface of the daughter board 405)is used for mounting the FPGA. The pads 482 are arranged in a squarearea 483 concentric with the connector 410 in plan view. The square area483 is split into four sectors by its diagonals; particularly, a topsector 483 t is subtended by an edge of the square area facing theconnector element 410 t (in plan view), a right sector 483 r issubtended by an edge facing the connector element 410 r, a left sector483 l is subtended by an edge facing the connector element 410 l, and abottom sector 483 b is subtended by an edge facing the connector element410 b. A further matrix of pads 485 is used for mounting the E²PROM; thepads 485 are arranged close to the second free end of the connectorelement 410 l and to the first free end of the connector element 410 b.

The pads 482 of each sector 483 t-483 b are connected to correspondingpins 476 of the facing connector elements 410 t-410 b (in plan view).Most of the pads 482 (for functional terminals of the FPGA) are used toexchange input/output signals with corresponding input/output terminalsof the FPGA; the remaining pads 482 are used to exchange control signalswith corresponding control terminals of the FPGA. The pads 482 forcontrol terminals of the FPGA are arranged around a centre of each edgeof the square area 483. The pads 482 for input/output terminals areconnected to the pins 476 of the corresponding connector elements 410t-410 b starting from the first free end (from pin 1 to pin 222); thepads 482 for control terminals are connected to the pins 476 of thecorresponding connector elements 410 t-410 b starting from the secondfree end (from pin 228 back to pin 223).

More specifically, the sector 483 t includes four pads 482 for controlterminals, each one used for supplying a different clock signal to theFPGA (CLK1, CLK2, CLK3 and CLK4). These pads are connected to the pinsfrom 228 to 225 of the connector element 410 t through a conductivetrack 488 t (with the pins 224 and 223 that are reserved for futureuse); all the conductive tracks 488 t have the same length (for example75 mm).

The sector 483 r includes four pads 482 for control terminals. The padconnected to the pin 228 of the connector element 410 r is used forproviding a signal PLUG_PRESENT to the mother board; the signalPLUG_PRESENT indicates the mounting of the daughter board when asserted(for example at a reference voltage, or ground). The pad connected tothe pin 227 is used for a reset signal JTRST of a JTAG (Joint TestAccess Group) interface of the FPGA. The pad connected to the pin 226 isused for supplying a system reset signal SYS_RESET to the FPGA. The padconnected to the pin 225 is used for providing a signal FPGA_DONE to themother board; the signal FPGA_DONE indicates the completion of loadingof the configuration data from the E²PROM (started automatically as soonas the FPGA is turned on or forced by means of a signal FPGA_PROGRAM).The pins 224 and 223 are reserved for future use.

The sector 483 l includes five pads 482 for control terminals. The padsconnected to the pins 228, 227, 226 and 225 of the connector element 410l are used for an input signal JTDI, an output signal JTDO, a test modeselection signal JTTMS, and a dedicated clock signal JTCLK of the JTAGinterface of the FPGA, respectively. The pad connected to the pin 224 isused for providing the signal FPGA_PROGRAM to the daughter board; thesignal FPGA_PROGRAM triggers a (warm) re-loading of the configurationdata from the E²PROM. The pin 223 is reserved for future use.

In a similar manner, five of the pads 485 are used for connection to aJTAG interface of the E²PROM. The pads 482 and the pads 485 for the JTDIand JTDO signals are connected in series to form a JTAG chain. Thesignals JTRST, JTTMS and JTCLK are supplied to both the FPGA and theE²PROM; particularly, the pin 226 (signal JTTMS) and the pin 225 (signalJTCLK) of the connector element 410 l are coupled with the respectivepads 482 and 485 through a conductive track 491 having a balanced treestructure.

The sector 483 b includes four pads 482 for control terminals, each oneused for supplying a different clock signal to the FPGA (CLK5, CLK6,CLK7 and CLK8). These pads are connected to the pins from 228 to 225 ofthe connector element 410 b through conductive tracks 488 b of the samelength (with the pins 224 and 223 that are reserved for future use).

As shown in the partially cut away view of the figure, the daughterboard 405 has a multi-layer structure. A power supply plane 494 pprovides a power supply voltage of +3.3V with respect to a correspondingground plane 494 g. The fifth and the sixth power male elements of eachconnector element 410 t-410 b are coupled to the power supply plane 494p and to the ground plane 494 g, respectively. In a similar manner, apower supply plane 495 p provides a power supply voltage of +5V withrespect to a corresponding ground plane 495 g. The third and the fourthpower male elements of each connector element 410 t-410 b are coupled tothe power supply plane 495 p and to the ground plane 495 g,respectively.

A further power supply plane is split into two portions 496 pa and 496pb along a diagonal of the daughter board 405 (not running across thereference key 417); a corresponding ground plane is likewise split intotwo portions 496 ga and 496 gb. The portion 496 pa provides a powersupply voltage of +12V and the portion 496 pb provides a power supplyvoltage of −12V relative to the portion 496 ga and to the portion 496gb, respectively, of the ground plane. The first and the second powermale elements of the connector elements 410 t and 410 l are coupled withthe portion 496 pa (+12V) and to the portion 496 ga, respectively; thefirst and the second power male elements of the connector elements 410 rand 410 b are coupled with the portion 496 pb (−12V) and with theportion 496 gb, respectively.

Moreover, a still further plane is split into a power supply portion 497p and a ground portion 497 g, which are coupled to the converter 440 a;the portion 497 p provides a power supply voltage of +1.8V relative tothe portion 497 g. In a similar manner, another plane is split into apower supply portion 498 p and a ground portion 498 g, which are coupledto the converter 440 b; the portion 498 p provides a power supplyvoltage of +2.5V relative to the portion 498 g.

In brief, the pin-out of the connector 410 is defined by the followingtables:

1 . . . 222 223 224 225 226 227 228 410t I/O Reserved Reserved CLK4 CLK3CLK2 CLK1 410r I/O Reserved Reserved FPGA_DONE SYS_RESET JTRSTPLUG_PRESENT 410l I/O Reserved FPGA_PROGRAM JTTMS JTCLK JTDO JTDI 410bI/O Reserved Reserved CLK8 CLK7 CLK6 CLK5

Element/pin 229 . . . 233, 234 . . . 238 239 . . . 243 244 . . . 248 249. . . 253 254 . . . 258 410t +12 V 0 (−12 V) +5 V 0 (+5) +3.3 0 (+3.3)410r −12 V 0 (+12 V) +5 V 0 (+5) +3.3 0 (+3.3) 410l +12 V 0 (−12 V) +5 V0 (+5) +3.3 0 (+3.3) 410b −12 V 0 (+12 V) +5 V 0 (+5) +3.3 0 (+3.3)

Similar considerations apply if the connector has a different structure,if each connector element is of the female type or includes a differentnumber of leads, if each power male element consists of a differentnumber of blades (down to a single one), if the E²PROM is placedelsewhere, if the daughter board has a different number of power supplyplanes, if different power supply voltages are used, if two or morepower supply planes are split into portions providing opposed voltages,and the like.

A different type of daughter board 505 to be mounted onto the motherboard is depicted in FIG. 5. A connector similar to the one describedabove is arranged on a lower surface of the daughter board 505. Theconnector is square-shaped and has a top element 510 t and a rightelement 510 r moving counter clockwise from a reference key 517 (for theinsertion key of a corresponding socket of the mother board), and a leftelement 510 l and a bottom element 510 b moving clockwise from thereference key 517. A socket consisting of two parallel elements 515 aand 515 b is arranged on an upper surface of the daughter board 505.Each connector element consists of 228 pins and 6 power male elements(matching a corresponding socket of the mother board), and each socketelement consists of 228 holes and 6 power female elements. The powermale elements of the connector 510 are coupled with the correspondingpower female elements of the socket 515 (through conductive tracks andvia-holes).

A microprocessor 520, an E²PROM 525 and a SRAM 540 are mounted on theupper surface of the daughter board 505, inside the connector 510 inplan view. Particularly, the daughter board 505 is provided with aplurality of conductive pads for surface mounting correspondingterminals of the microprocessor 520, the E²PROM 525 and the SRAM 540.The memory 525 stores a program controlling the microprocessor 520, andthe memory 540 is used by the microprocessor 520 as a working memory.The microprocessor 520 has a reference corner (identified by a chamfer),which faces the reference key 517.

Memory modules 550 a and 550 b (such as of the DIMM type) are pluggedinto the respective socket elements 515 a and 515 b; each memory module550 a, 550 b consists of a board that carries several DRAMs and isprovided with an edge connector (matching the socket element 515 a, 515b).

Some pads of the daughter board 505 (on which the microprocessor 520 ismounted) are connected to corresponding pins of the connector 510,whereas some other pads are connected to corresponding holes of thesocket 515. In this way, a first sub-set of functional terminals of themicroprocessor 520 is coupled with the memory modules 550 a, 550 b and asecond sub-set of functional terminals of the microprocessor 520 iscoupled with the connector 510.

The daughter board described above allows standard devices to be readilyinserted into the prototyping system. Similar considerations apply ifthe daughter board has a different structure, if the socket has adifferent number of elements or if the daughter board has no socket, ifthe microprocessor is replaced by an I/O device (or one or moreequivalent not-hardware programmable devices), if the memory modules areof a different type (such as SIMMs), and the like.

With reference now to FIG. 6, the daughter boards 405 and 505 aremounted onto the mother board 115; the connector 410 is plugged into thesocket 210 a and the connector 510 is plugged into the socket 210 b. Theauxiliary board 450 is mounted onto the daughter board 405.Particularly, the connector element 455 is plugged into the socketelement 415 t; no auxiliary board is plugged into the other socketelements (such as the socket element 415 b shown in the figure).

In this case, an extender board 605 is employed; the extender board hasa connector element 610 (arranged on a lower surface thereof) and anopposed socket element 615 (arranged on an upper surface thereof). Theconnector element 610 consists of 228 pins (without any power element)and the socket element 615 consists of 228 holes (without any powerelement). The pins of the connector element 610 are coupled with thecorresponding holes of the socket element 615 through via-holes.

The system further includes a debugging board 620, which is mounted ontop of the above described stack. Multiple connectors 625 are arrangedon a lower, surface of the debugging board 620, and multiple sockets 630are arranged on an upper surface thereof. Each connector 625 issquare-shaped, with four elements (each one consisting of 228 pins)matching corresponding socket elements 455 or 610. Each socket 630includes several holes for plugging in corresponding probe terminalsconnected to the host computer (not shown in the figure). The connectors625 and the sockets 630 are coupled (though conductive tracks andvia-holes) with a switch matrix 635 (mounted on the upper surface of thedebugging board 620); the switch matrix 635 selectively connects eachpin of the connectors 625 to a corresponding hole of the sockets 630.

The particular structure of the auxiliary boards facilitates the use ofthe debugging board. Moreover, the extender boards allow the debuggingboard to be readily connected to the system even when one or more socketelements of the daughter board are free.

Each time the design of an electronic circuit under validation has beenscattered across several FPGAs, these FPGAs are mounted ontocorresponding daughter boards. The local resources for each FPGA (i.e.,the memory modules) are mounted onto auxiliary boards, which are pluggedinto the daughter board carrying the FPGA. The other devices (such asmicroprocessors and I/O units) defining a real world target system inwhich the electronic circuit must operate are mounted onto differentdaughter boards. All the daughter boards (carrying the FPGAs or theother devices) are plugged into corresponding sockets of the motherboards. The mother boards are then mounted onto the back-plane (togetherwith the other system boards).

The system is connected to the host computer controlling the prototypingprocess. Particularly, configuration data for the FPGAs and the programscontrolling the microprocessors are downloaded into the correspondingmemories. In a similar manner, the memories associated with each socketof the mother boards are loaded with configuration data for therespective switches, in order to define the required connectivity of thesystem.

More specifically, when an auxiliary board is plugged into a socketelement of the daughter board, the corresponding switches on the motherboard are both open, so that the holes of the socket on the motherboard, and then also the terminals of the FPGA, are only connected tothe terminals of the local resources mounted onto the auxiliary board(being insulated from the connections of the mother board). Conversely,when a socket element of the daughter board is free, one or more of thecorresponding switches on the mother board are closed, so that the holesof the socket on the mother board, and then also the terminals of theFPGA, are coupled with the selected connections on the mother board; asa consequence, the FPGA is connected to another FPGA or to a differentdevice either on the same mother board (through a point-to-pointconnection) or on a different mother board (through a bus of theback-plane, a cross-bar board of the back-plane, or a flexible printedcircuit).

Similar considerations apply if the extender board and the debuggingboard have a different structure, if the socket of the debugging boardhas a different number of holes (for the probe terminals), if the holesof the socket and the pins of the connector on the debugging board areconnected in a different manner, and the like. Alternatively, theauxiliary boards have a different structure (for example of the SIMM orDIMM type), a different connection of the debugging board is envisaged(even without any extender board), probing-plugs are directly providedon the mother board and daughter boards, and the like.

More generally, the present invention provides a daughter board for aprototyping system. The daughter board has a first surface for facing amother board of the prototyping system and a second surface opposedthereto. A connector for a corresponding socket of the mother board isarranged on the first surface; the connector consists of a plurality ofelements, each one including an insulating support and a plurality ofleads. Multiple contacts for corresponding functional terminals of aprogrammable device are arranged on the second surface; each contact isconnected to a corresponding lead of the connector. The elements of theconnector are arranged along the edges of a regular polygon.

The structure of the daughter board according to the present inventionhas been found to be specifically suitable for use in a prototypingsystem.

Particularly, the devised arrangement of the connector elements makes itpossible to optimise the signal transmission both on the daughter boardand on the corresponding mother board. This results in a substantialisotropic and very low (for example of a few ns) transmission delay inthe whole prototyping system. As a consequence, the prototyping systemruns at the same speed as the actual electronic circuit (for example inthe order of 100 MHz), so that the prototype can be operated and testedunder normal working conditions.

The preferred embodiment of the invention described above offers furtheradvantages.

Particularly, the daughter board includes a further socket for localresources that are used by the FPGA; each pad for the FPGA is connectedto both the connector and the socket of the daughter board. Thissolution makes it possible to place the local resources directly wherethey are used (by the FPGAs).

However, the solution according to the present invention leads itself tobe used even in a different daughter board, such as the one describedabove for the microprocessors and the I/O units.

Preferably, the connector is square-shaped, with two connector elementsthat are arranged clockwise and the other two connector elements thatare arranged counter clockwise (from the reference key). Thisarrangement of the connector elements has been found to be the preferredtopology of the daughter board; moreover, the corresponding sockets onthe mother board (arranged at the corners of a rectangle, with theinsertion keys inward-looking the rectangle) optimise the routing of thesignals, thereby reducing the number of layers required in the motherboard.

Alternatively, the connector elements are arranged along a differentregular polygon (such as a triangle, a pentagon, and so on), thedaughter board is used with a mother board having a different number ofsockets (down to a single socket) or with the sockets turneddifferently.

The pads of the daughter board used by the FPGA are grouped in severalsectors; the pads of each sector are connected to the pins of thecorresponding connector element. Therefore, each pad is directlyconnected to the respective pin with an optimised path; this structureimproves the performance of the daughter board (and then of the wholeprototyping system).

The pads for input/output terminals of the FPGA are connected to asub-set of the pins starting from the free end of the correspondingconnector element identified by the reference key; the pads for controlterminals are connected to a further sub-set of the pins starting fromthe other free end of the connector element opposed to the referencekey. The arrangement of consecutive pins in two subsets (starting fromopposed free ends of the connector element) is particularly advantageousfor programming and debugging purposes; moreover, the proposed featureis very flexible and allows the daughter board to be readily adapted toFPGAs having a higher number of terminals.

The pads for clock terminals of the FPGA are arranged around the centreof the edge of the top and bottom sectors, and they are connected to thepins of the corresponding connector element starting from the free endopposed to the reference key; the connection is made with conductivetracks having the same length. This structure does not provide theshortest path for the clock signals on the daughter board (as it wouldbe if the pads for the clock signals were connected to the central pinsof the corresponding connector element); however, the inventors havediscovered that the proposed arrangement surprisingly yields to higherperformance of the whole prototyping system, due to the improved routingof the clock signals on the mother board.

The pin of the left connector element transmitting the JTCLK signal isconnected to the corresponding pads for the FPGA and for the E²PROMthrough a conductive track having a balanced tree structure. Thisensures an optimal distribution of this signal to both the FPGA and theE²PROM.

Alternatively, the pads are arranged in an area with a different shape(and then with a different number of sectors), the pads for input/outputterminals and for control terminals are in a different number, adifferent number of clock signals are used, the JTAG interface isreplaced by an equivalent serial test interface, and the like. However,the solution of the invention leads itself to be implemented even withthe pads connected to the corresponding pins in a different manner, withdifferent control terminals of the FPGA, with a single clock signal oreven without any JTAG interface.

Each power supply plane is connected to corresponding blades of eachconnector element. In this way, the power supply plane is contacted inmultiple points, so as to ensure a uniform distribution of therespective power supply voltage to the FPGA.

The sectioning of the power supply plane providing the opposed powersupply voltages of +12V and −12V yields to a structure that is veryflexible and compact at the same time.

Alternatively, the power supply is distributed to the daughter board ina different way, the power supply planes are split in a differentmanner, or every power supply plane provides a single power supplyvoltage.

The prototyping system using the daughter boards of the presentinvention substantially reduces the time required for setting up a newprototype (when compared with the one required by a breadboard).Moreover, the system can be re-used for different prototypes, so thatthe investment required can be recovered in a short time.

The envisaged solution is very flexible, since the connectivity schemecan be readily altered. This result is obtained with a structure onwhich not any prototype can be fitted, since a completeinterconnectivity is not provided. However, the inventors have devised astructure that accommodates the most ordinary characteristics that havebeen identified among several design categories, so that most of theelectronic circuits can be tested with the proposed prototyping system.

However, the daughter board of the invention leads itself to be usedeven in a different prototyping system, for example with the switchesplaced on each daughter board (for selectively connecting the terminalsof the FPGA either to the socket or to the connector and then to apoint-to-point connection on the mother board, hardwired coupledthereto).

Naturally, in order to satisfy local and specific requirements, a personskilled in the art may apply to the solution described above manymodifications and alterations, all of which, however, are includedwithin the scope of protection of the invention as defined by thefollowing claims.

1. A daughter board for a prototyping system, said daughter boardcomprising: a first surface for facing a mother board of the prototypingsystem and a second surface opposed thereto; a connector for acorresponding socket of the mother board, the connector being arrangedon the first surface of the daughter board and including a plurality ofelements, each of the elements including an insulating support and aplurality of leads; and a plurality of contacts for correspondingfunctional terminals of a programmable device, the contacts beingarranged on the second surface of the daughter board, each of thecontacts being connected to a corresponding lead of the connector,wherein the elements of the connector are arranged along the edges of aregular polygon, each element of the connector includes a first and asecond sub-set of leads connected to corresponding contacts forinput/output terminals and control terminals of the programmable device,the contacts for control terminals of each sector being arranged arounda center of a corresponding edge of a regular polygonal area, and thefirst sub-set and the second sub-set are arranged starting from a firstfree end and from a second free end, respectively, of each element ofthe connector.
 2. The daughter board according to claim 1, furtherincluding a further socket arranged on the second surface for connectinglocal resources associated with the programmable device, each contactbeing further connected to a corresponding lead of the further socket.3. The daughter board according to claim 1, wherein the regular polygonis a square, the elements of the connector include a first and a secondelement arranged counter clockwise on the first surface from a mountingreference of the daughter board, and a third and a fourth elementarranged clockwise on the first surface from the mounting reference, andeach element of the connector has a first and a second free end movingalong the corresponding direction from the mounting reference.
 4. Thedaughter board according to claim 1, wherein the contacts are arrangedin a regular polygonal area concentric with the regular polygon in planview, the regular polygonal area including a plurality of sectors eachone facing a corresponding element of the connector in plan view, andthe contacts of each sector are connected to the leads of thecorresponding element of the connector.
 5. The daughter board accordingto claim 3, wherein the contacts for control terminals of the sectorcorresponding to the first and the fourth element of the connector arefor clock terminals of the programmable device, the contacts for clockterminals being connected to the corresponding leads through conductivetracks having the same length.
 6. The daughter board according to claim3, wherein the contacts for control terminals of the sectorcorresponding to the third element include a contact for a test clockterminal of the programmable device, the corresponding lead beingconnected to the contact for the test clock terminal and to a furthercontact for a test clock terminal of a configuration memory of theprogrammable device through a further conductive track having a balancedtree structure.
 7. The daughter board according to any claim 1, furtherincluding a plurality of power supply planes each one for providing acorresponding power supply voltage, each power supply plane beingconnected to at least one corresponding lead of each element of theconnector.
 8. A daughter board for a prototyping system, said daughterboard comprising: a first surface for facing a mother board of theprototyping system and a second surface opposed thereto; a connector fora corresponding socket of the mother board, the connector being arrangedon the first surface of the daughter board and including a plurality ofelements, each of the elements including an insulating support and aplurality of leads; and a plurality of contacts for correspondingfunctional terminals of a programmable device, the contacts beingarranged on the second surface of the daughter board, each of thecontacts being connected to a corresponding lead of the connector,wherein the elements of the connectors are arranged along the edges ofregular polygon, and the daughter board further comprises: a pluralityof power supply planes each one for providing a corresponding powersupply voltage, each power supply plane being connected to at least onecorresponding lead of each element of the connector; and at least onefurther power supply plane split into a first and a second portion forproviding a first power supply voltage and a second power supply voltageopposed to the first power supply voltage, the first portion of thefurther power supply plane being connected to at least one correspondinglead of the first and third element of the connector, and the secondportion of the further power supply plane being connected to at leastone corresponding lead of the second and fourth element of theconnector.
 9. A prototyping system comprising: at least one mother boardhaving a plurality of sockets; a plurality of point-to-point connectionsfor pairs of the sockets; and at least one daughter board comprising: afirst surface for facing the mother board of the prototyping system anda second surface opposed thereto; a connector for a corresponding socketof the mother board, the connector being arranged on the first surfaceof the daughter board and including a plurality of elements, each of theelements including an insulating support and a plurality of leads; aplurality of contacts for corresponding functional terminals of aprogrammable device, the contacts being arranged on the second surfaceof the daughter board, each of the contacts being connected to acorresponding lead of the connector; and a further socket arranged onthe second surface of the daughter board for connecting local resourcesassociated with the programmable device, each contact being furtherconnected to a corresponding lead of the further socket, wherein theelements of the connector are arranged along the edges of a regularpolygon, wherein the connector of each daughter board is plugged into acorresponding socket, and a plurality of electronic switches arearranged on the mother board for selectively connecting each lead of thesocket to a corresponding lead of the point-to-point connections. 10.The prototyping system according to claim 9, wherein the regular polygonof the daughter board is a square, the elements of the connector of thedaughter board include a first and a second element arranged counterclockwise on the first surface from a mounting reference of the daughterboard, and a third and a fourth element arranged clockwise on the firstsurface from the mounting reference, and each element of the connectorof the daughter board has a first and a second free end moving along thecorresponding direction from the mounting reference.
 11. The prototypingsystem according to claim 10, wherein the contacts for control terminalsof the sector corresponding to the first and the fourth element of theconnector of the daughter board are for clock terminals of theprogrammable device, the contacts for clock terminals being connected tothe corresponding leads through conductive tracks having the samelength.
 12. The prototyping system according to claim 10, wherein thecontacts for control terminals of the sector corresponding to the thirdelement of the daughter board include a contact for a test clockterminal of the programmable device, the corresponding lead beingconnected to the contact for the test clock terminal and to a furthercontact for a test clock terminal of a configuration memory of theprogrammable device through a further conductive track having a balancedtree structure.
 13. The prototyping system according to claim 9, whereinthe contacts of the daughter board are arranged in a regular polygonalarea concentric with the regular polygon in plan view, the regularpolygonal area including a plurality of sectors each one facing acorresponding element of the connector in plan view, and the contacts ofeach sector of the daughter board are connected to the leads of thecorresponding element of the connector.
 14. The prototyping systemaccording to claim 9, wherein each element of the connector of thedaughter board includes a first and a second sub-set of leads connectedto corresponding contacts for input/output terminals and controlterminals of the programmable device, the contacts for control terminalsof each sector being arranged around a center of a corresponding edge ofa regular polygonal area, and the first sub-set and the second sub-setare arranged starting from a first free end and from a second free end,respectively, of each element of the connector.
 15. The prototypingsystem according to claim 9, wherein the daughter board further includesa plurality of power supply planes each one for providing acorresponding power supply voltage, each power supply plane beingconnected to at least one corresponding lead of each element of theconnector.
 16. The prototyping system according to claim 15, thedaughter board further includes at least one further power supply planesplit into a first and a second portion for providing a first powersupply voltage and a second power supply voltage opposed to the firstpower supply voltage, the first portion of the further power supplyplane being connected to at least one corresponding lead of the firstand third element of the connector, and the second portion of thefurther power supply plane being connected to at least one correspondinglead of the second and fourth element of the connector.